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<a href="#define-members">Macros</a> &#124;
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Macros</h2></td></tr>
<tr class="memitem:ga0756f011ef667460d583017366823244"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga0756f011ef667460d583017366823244">DEFAULT_PRIORITY</a>&#160;&#160;&#160;0xa0a0a0a0U</td></tr>
<tr class="memdesc:ga0756f011ef667460d583017366823244"><td class="mdescLeft">&#160;</td><td class="mdescRight">Default value for priority_level register.  <a href="group__scugic__api.html#ga0756f011ef667460d583017366823244">More...</a><br/></td></tr>
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Functions</h2></td></tr>
<tr class="memitem:ga2cbf5d5ac5273e00c0b16bd33ad0707f"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga2cbf5d5ac5273e00c0b16bd33ad0707f">XScuGic_DeviceInitialize</a> (u32 DeviceId)</td></tr>
<tr class="memdesc:ga2cbf5d5ac5273e00c0b16bd33ad0707f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initializes the GIC based on the device ID.  <a href="group__scugic__api.html#ga2cbf5d5ac5273e00c0b16bd33ad0707f">More...</a><br/></td></tr>
<tr class="separator:ga2cbf5d5ac5273e00c0b16bd33ad0707f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga96bfe161e3b4e401f76f2b35df9fab86"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga96bfe161e3b4e401f76f2b35df9fab86">XScuGic_DeviceInterruptHandler</a> (void *DeviceId)</td></tr>
<tr class="memdesc:ga96bfe161e3b4e401f76f2b35df9fab86"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is the primary interrupt handler for the driver.  <a href="group__scugic__api.html#ga96bfe161e3b4e401f76f2b35df9fab86">More...</a><br/></td></tr>
<tr class="separator:ga96bfe161e3b4e401f76f2b35df9fab86"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac1d1444968ff82f78505eeae32a2e471"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gac1d1444968ff82f78505eeae32a2e471">XScuGic_RegisterHandler</a> (UINTPTR BaseAddress, s32 InterruptID, Xil_InterruptHandler IntrHandler, void *CallBackRef)</td></tr>
<tr class="memdesc:gac1d1444968ff82f78505eeae32a2e471"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register a handler function for a specific interrupt ID.  <a href="group__scugic__api.html#gac1d1444968ff82f78505eeae32a2e471">More...</a><br/></td></tr>
<tr class="separator:gac1d1444968ff82f78505eeae32a2e471"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac8e95bba26e2b07a882cb03750540b4d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gac8e95bba26e2b07a882cb03750540b4d">XScuGic_SetPriTrigTypeByDistAddr</a> (UINTPTR DistBaseAddress, u32 Int_Id, u8 Priority, u8 Trigger)</td></tr>
<tr class="memdesc:gac8e95bba26e2b07a882cb03750540b4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the interrupt priority and trigger type for the specificd IRQ source.  <a href="group__scugic__api.html#gac8e95bba26e2b07a882cb03750540b4d">More...</a><br/></td></tr>
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<tr class="memitem:ga19437ca93adc808161232c5667d7ca62"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga19437ca93adc808161232c5667d7ca62">XScuGic_GetPriTrigTypeByDistAddr</a> (UINTPTR DistBaseAddress, u32 Int_Id, u8 *Priority, u8 *Trigger)</td></tr>
<tr class="memdesc:ga19437ca93adc808161232c5667d7ca62"><td class="mdescLeft">&#160;</td><td class="mdescRight">Gets the interrupt priority and trigger type for the specificd IRQ source.  <a href="group__scugic__api.html#ga19437ca93adc808161232c5667d7ca62">More...</a><br/></td></tr>
<tr class="separator:ga19437ca93adc808161232c5667d7ca62"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaadf6b084a0540093dd64b8a8e3e74d6c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaadf6b084a0540093dd64b8a8e3e74d6c">XScuGic_InterruptMapFromCpuByDistAddr</a> (UINTPTR DistBaseAddress, u8 Cpu_Id, u32 Int_Id)</td></tr>
<tr class="memdesc:gaadf6b084a0540093dd64b8a8e3e74d6c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the target CPU for the interrupt of a peripheral.  <a href="group__scugic__api.html#gaadf6b084a0540093dd64b8a8e3e74d6c">More...</a><br/></td></tr>
<tr class="separator:gaadf6b084a0540093dd64b8a8e3e74d6c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga51ba67d5953cb6b68a8d327b5e3103d7"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga51ba67d5953cb6b68a8d327b5e3103d7">XScuGic_InterruptUnmapFromCpuByDistAddr</a> (UINTPTR DistBaseAddress, u8 Cpu_Id, u32 Int_Id)</td></tr>
<tr class="memdesc:ga51ba67d5953cb6b68a8d327b5e3103d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Unmaps specific SPI interrupt from the target CPU.  <a href="group__scugic__api.html#ga51ba67d5953cb6b68a8d327b5e3103d7">More...</a><br/></td></tr>
<tr class="separator:ga51ba67d5953cb6b68a8d327b5e3103d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac7192c00a59e0cca27ed4c46f2755bb0"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gac7192c00a59e0cca27ed4c46f2755bb0">XScuGic_UnmapAllInterruptsFromCpuByDistAddr</a> (UINTPTR DistBaseAddress, u8 Cpu_Id)</td></tr>
<tr class="memdesc:gac7192c00a59e0cca27ed4c46f2755bb0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Unmaps all SPI interrupts from the target CPU.  <a href="group__scugic__api.html#gac7192c00a59e0cca27ed4c46f2755bb0">More...</a><br/></td></tr>
<tr class="separator:gac7192c00a59e0cca27ed4c46f2755bb0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadaa95193630e661a6a578f35a5e3ea1a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gadaa95193630e661a6a578f35a5e3ea1a">XScuGic_EnableIntr</a> (UINTPTR DistBaseAddress, u32 Int_Id)</td></tr>
<tr class="memdesc:gadaa95193630e661a6a578f35a5e3ea1a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the interrupt source provided as the argument Int_Id.  <a href="group__scugic__api.html#gadaa95193630e661a6a578f35a5e3ea1a">More...</a><br/></td></tr>
<tr class="separator:gadaa95193630e661a6a578f35a5e3ea1a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0d183d23d05aac5d61cd640c5b39b275"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga0d183d23d05aac5d61cd640c5b39b275">XScuGic_DisableIntr</a> (UINTPTR DistBaseAddress, u32 Int_Id)</td></tr>
<tr class="memdesc:ga0d183d23d05aac5d61cd640c5b39b275"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disables the interrupt source provided as the argument Int_Id so that the interrupt controller will not cause interrupts for the specified Int_Id.  <a href="group__scugic__api.html#ga0d183d23d05aac5d61cd640c5b39b275">More...</a><br/></td></tr>
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